1. Field of the Invention
The present invention relates to semiconductor devices and methods of fabricating same. More particularly, the invention relates to semiconductor devices having recessed gate electrodes and methods of fabricating same.
2. Discussion of Related Art
As electronic products employing semiconductor devices have become increasingly thin, lightweight, and compact, semiconductor devices used in such produce generally have been required to become more densely integrated. Accordingly, research for reducing the two-dimensional size of transistors has been ongoing.
Reduction in transistor size has resulted in the reduction of transistor channel length and channel width. However, the drive current provided by a transistor is inversely proportional to its channel length, and generally proportional to its channel width. Thus, reduction in channel length may increase drive current and response speed. In contrast, reduction in channel length may cause problems, such as punch-through. Consequently, there is a continuing need for design and fabrication approaches that minimize the two-dimensional size of transistors while at the same time providing an effective channel length.
One type of transistor known as a recess channel array transistor (RCAT) accomplishes these two objectives. The RCAT allows reduction in two-dimensional size while effectively increasing channel length. To fabricate a RCAT, a gate trench is first formed in an active region of a constituent substrate. An insulated gate electrode is formed to cross the active region and fill the gate trench. In this manner, the depth of the gate trench increases the effective channel length.
Early RCATs were fabricated with a gate electrodes having planar shapes (i.e., shapes defined by linear geometries). See, for example U.S. Pat. No. 7,157,770, the subject matter of which his hereby incorporated by reference.
However, later RCAT designs departed from strictly planar shapes to include curved shapes (i.e., shapes defined in whole or in part by an arc). One of these design alternative is the spherical recess channel array transistor (SRCAT). The SRCAT like all RCAT designs increases the effective channel length. In the SRCAT, a planar upper gate trench is formed in an active region of a substrate. A curved lower gate trench is formed (e.g.,) in the shape of a flask below the upper planar gate trench. An insulated gate electrode is formed to cross the active region and fill the upper and lower gate trenches. The combined depth of the upper and lower gate trenches serves to increase the effective channel length of the transistor.
As noted above, reduction in channel width typically decreases the drive current provided by a transistor. Thus, channel width is designed in consideration of the drive current required for the operation of the semiconductor device incorporating the transistor. Accordingly, various design and fabrication techniques have been applied to extend the effective channel width.
FIG. 1 is a cross-sectional view of a conventional RCAT. The first region “1” of FIG. 1 shows a cross-section of the RCAT taken in a word line direction. The second region “2” of FIG. 1 is a cross-section of the RCAT taken in a bit line direction. Referring to FIG. 1, the conventional RCAT includes an isolation layer 16 defining an active region 13 within a semiconductor substrate 11. In the illustrated example, isolation layer 16 includes an insulating layer 15 formed on a sidewall oxide layer 14. A gate trench 17 is formed in active region 13. Gate trench 17 crosses active region 13 and partially exposes sidewalls of isolation layer 16. A gate electrode 19 is formed across active region 13. Gate electrode 19 has a descending gate electrode portion 19E extending into gate trench 17. A gate dielectric layer 18 is interposed between active region 13 and gate electrode 19. Gate dielectric layer 18 is also interposed between active region 13 and descending gate electrode portion 19E. Source/drain regions 21 and 23 are formed in active region 13 at respective sides of gate electrode 19.
The effective channel length “CL1” of the RCAT illustrated in FIG. 1 is relatively long compared to a conventional planar transistor because of the presence of gate trench 17. Accordingly, even when the two-dimensional size of the RCAT is reduced, a desirable effective channel length CL1 may be secured.
However, an effective channel width “CW1” of the RCAT illustrated in FIG. 1 is yet dependent on the size of active region 13, and active region 13 is defined by isolation layer 16. In the illustrated example, to reduce the two-dimensional size of the RCAT, it is advantageous to reduce active region 13 to the resolution limit of the photolithography process used to fabricate the transistor. However, reduction of active region 13 may cause the effective channel width CW1 to be reduced. In this case, the drive current provided by the RCAT will also be reduced.
The width of active region 13 should be increased to increase the effective channel width CW1. Yet, this approach works against the design objective of increasing integration density for an array of RCATs.
One technique for increasing the effective channel width of a transistor is described in published U.S. Patent Application No. 2003/0085345, the subject matter of which is hereby incorporated by reference. According to this technique, at least one recess region is formed in a channel length direction of an active region. An insulated gate electrode is formed across the recess regions. The recess regions act to extend the effective channel width of the transistor. Another informative technique for forming a transistor is described in U.S. Pat. No. 6,844,591, the subject matter of which is hereby incorporated by reference.